AR# 10133


6.2 System Generator for DSP - How do I generate optimal control logic using System Generator?


General Description: 

What is available in System Generator for DSP v3.1 that can generate control logic for DSP designs?


All DSP applications require some sort of control logic in the design. Currently, System Generator provides numerous blocks and features that assist in control logic. Most System Generator blocks provide Clock Enable pins that you can use to control the points at which blocks execute. For blocks without CE pins, you can use the Vin (valid in) and Vout (valid out) pins to control the points at which data samples are valid or not, functioning in a manner similar to a CE pin. You can use Counters, Expression Blocks, State Machines, Relational blocks, and Logical blocks to generate any required control signals. You can use MATLAB code to describe state machines via the M-Code Block. For more information on the M-Code block, see the following section in the User Guide:

You can also use the CE Probe to expose the underlying Clock Enable circuitry that is used to generate multi-rate systems in the System Generator. Since there is only one clock domain in all System Generator designs, clock enables are used to create different rates in the designs. For example, if a block is running at 10 MHz and the System Rate (clock rate) is at 100 MHz, this block is enabled every ten clock cycles. The CE probe exposes these enable signals for the sampling rate of the section to which it is connected. Another option is to use the black box, which enables the incorporation of VHDL into the code that is generated. For more information on Black Boxes, see the following section of the User Guide:

AR# 10133
日期 05/14/2014
状态 Archive
Type 综合文章
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