AR# 10134

System Generator for DSP - Is it possible to pass user-defined constraints into the generated VHDL?

描述

General Description: 

Is it possible to pass user-defined constraints into the generated VHDL?

解决方案

No -- there is no current mechanism for passing user-defined constraints into the generated VHDL.

AR# 10134
日期 05/14/2014
状态 Archive
Type 综合文章