AR# 10167

14.x Timing - Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs? (Clock Uncertainty)

描述

Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs?

解决方案

DCM/PLL/MMCM jitter and phase errors are taken into account in the timing report for Virtex-4, Virtex-5, and Virtex-6 devices as Clock Uncertainty. No DCM jitter will be analyzed or reported for legacy device families that do not have characterized DCM jitter.
AR# 10167
日期 12/15/2012
状态 Active
Type 综合文章
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