After I assign a valid address to BARx, my Xilinx PCI device still does not respond to memory or I/O transactions as a target.
Memory Space Access
The Memory Space bit in the Command/Status Register needs to be set by the host system before the Xilinx PCI device will respond to memory space accesses.
I/O Space Access
The I/O Space bit in the Command/Status Register must be set by the host system before the Xilinx PCI device will respond to I/O space accesses.
The Command/Status register is located at offset 04h in the Configuration Space Header as illustrated below: