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3.4 FPGA Express - FPGA Express does not export clock pin lock constraint for 4k architectures.
Keywords: pin, lock, constraint, clock, 4k
FPGA Express normally exports pin-locking information in the EDIF netlist.
However, FPGA Express does not export pin-locking information for clock
ports in 4K architectures.
Use a UCF to lock the clock pins. Below is an example of the appropriate
UCF syntax for the LOC constraint:
NET clock LOC=P57;