AR# 10219


3.1i Virtex MAP - MULTAND usage leads to the error "Pack:679 - Unable to obey design constraints"


Keywords: MAP, pack, 679, MULTAND

Urgency: Standard

General Description:
MAP fails with the following pack error:

ERROR:Pack:679 - Unable to obey design constraints (MACRONAME = xmt_pil_dqm/pi_ins/mult_q/mult14x11ve/a1/toprow, RLOC = R3C1.S1) which require the combination of the following symbols into a single slice component:
LUT symbol "xmt_pil_dqm/pi_ins/mult_q/BU180" (Output Signal =
MULTAND symbol "xmt_pil_dqm/pi_ins/mult_q/BU181" (Output Signal =
MUXCY symbol "xmt_pil_dqm/pi_ins/mult_q/BU182" (Output Signal =
XORCY symbol "xmt_pil_dqm/pi_ins/mult_q/BU183" (Output Signal =
LUT symbol "xmt_pil_dqm/pi_ins/mult_q/BU184" (Output Signal =
XORCY symbol "xmt_pil_dqm/pi_ins/mult_q/BU185" (Output Signal =
The function generator xmt_pil_dqm/pi_ins/mult_q/BU180 is unable to be placed in the F position because there is a conflict for the F function generator input pins. Please correct the design constraints accordingly.

NOTE: This Answer record is only a good match for your issue if one of the symbols listed is a MULTAND.

This problem affects Virtex, Virtex-E and Spartan-II device families



This problem occurs when logic replication interferes with the necessary LUT/MULTAND connectivity, making the pack impossible. The work around is to run MAP with the switch "-l", which disables logic replication.

In this context, logic replication has nothing to do with fanout. This replication has to do with pushing logic forward into multiple LUT

This problem will be fixed in version 4.1i, which was released in August, 2001.


A variation of this error message has been seen when there were unconnected
I/Os in the user's HDL code.
AR# 10219
日期 08/19/2002
状态 Archive
Type 综合文章
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