General Description: A clock signal connected to the write clock of a CORE Generator FIFO cannot be constrained to a GCK pin, as the following error occurs during MAP:
"ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "PAD_NAMEx" (Pad Signal = PAD_NAMEx) BUF symbol "PAD_NAME_ibuf" (Output Signal = PAD_NAME_c) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "PAD_NAMEx" (LOC=A17) Please correct the constraints accordingly."
In the 3.1i software, the MAP error reads:
"Pack: 683 The symbol <> has constraint (LOC=XXX) that specifies an illegal physical site for the component."
This error has occurred when Synplicity is used as the synthesis tool.
The error occurs when Synplify instantiates an IBUF from the clock pad instead of an IBUFG. This happens because the clock signal is connected to a core, which is seen as a black box. Therefore, the synthesis tool cannot differentiate between a clock signal and a regular signal, and it simply instantiates an IBUF.
The solution is to instantiate the IBUFG in your HDL code.
You can also use the "syn_isclock" attribute to enable Synplify to recognize the clock. For more information on this, please see (Xilinx Answer 1561).