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AR# 10384

3.4 FPGA Express - Consumes too much memory and hard drive space every time I synthesize VHDL files.


Keywords: FPGA Express 3.4, memory, synthesis, VHDL

Urgency: Standard

General Description:
What can I do if my design is consuming too much memory and hard drive space?


Many memory issues that deal with large designs have been resolved
in an upcoming FPGA Express: Version 3.5.

If you are instantiating a component many times (in the hundreds), then
synthesize the component by itself (making sure to deselect Insert I/O)
so that you have an EDIF netlist. Then, instantiate the component as a
black box in your top level design.
AR# 10384
日期 08/21/2002
状态 Archive
Type 综合文章