A "clock period specification" checks the timing clocked by the net (all paths that terminate at a register clocked by the specified net). The clock period specification is used to define the allowable time for paths between elements clocked by the flagged clock signal. The period specification covers all data paths between synchronous elements.
The period specification is attached to the clock net. The definition of a clock period differs from a FROM:TO style specification in that the timing analysis tools automatically take into account any inversions of the clock net at register clock pins.
A PERIOD constraint on the clock net in the following figure generates a check for delays on all paths that terminate at a pin with a setup or hold timing constraint relative to the clock net. This can include the data paths D1 to CLB1.D and CLB1.Q to CLB2.D, as well as EN to CLB2.EC (if the enable were synchronous with respect to the clock).
Beginning in the 3.1i software, the timing tool no longer checks pad-to-register paths relative to setup requirements. For example, in the preceding figure, the path from D1 to Pin D of CLB1 is no longer included in the PERIOD constraint.
Consequently, every design should include a PERIOD constraint that covers all clocks in the design.
For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf