AR# 10429: 14.x Constraints - When should I use a TIG (Timing Ignore) constraint?
14.x Constraints - When should I use a TIG (Timing Ignore) constraint?
When should I use a TIG constraint in my design?
In a design, some paths do not require timing analysis. These are paths that exist in the design but are never used during time-critical operations. If you indicate a timing requirement on these paths, more important paths might be slower, which can result in a failure to meet the timing requirements.
The value of TIG can be the following:
- Empty (global TIG that blocks all paths) - A single TSid to block
If this attribute is attached to a net, primitive pin, or macro pin, all paths that fan forward from the point of application of the attribute are treated as if they do not exist for the purposes of timing analysis during implementation. In the following figure, NET C is ignored. However, note that the lower path of NET B that runs through the two OR gates would not be ignored.
Xilinx recommends placing TIG constraints on non-time-critical paths (e.g., paths that do not need a timing requirement or are very slow). The paths that go between non-critical clock domains are considered "False Paths" and can be placed in a TIG constraint. For more details on timing constraints, please see the Timing Constraints User Guide:http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf