General Description: When performing a Timing Simulation on a CPLD design, flip-flops outputs go into undefined states, even though the Functional Simulation was successful.
The Foundation Simulator does not toggle the PRLD signal during the Power-on/ Reset initialization; the PRLD signal is present in the post-fitted netlist, so if this signal is not toggled at the beginning of the simulation, the flip-flops are will not be properly initialized.
At the beginning of the simulation, toggle the PRLD signal.
Add the signal "PRLD" to the Waveform Viewer Window. PRLD is active-high, so drive it high, then low, at the start of the simulation to initialize all the flip-flops.
The PRLD signal should be toggled automatically in Foundation Logic Simulator versions 1.5 and later.