We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10453

CPLD XC9500/XL/XV CoolRunner-II/XPLA3 - How to use global resources (GCK, GTS, GSR)


CPLDs contain pins which are connected to dedicated routing for certain functions: clocking (GCK), set/reset (GSR), and output enable (GTS).  

These pins also have general purpose I/O capability, so how do I ensure that the pin is using the dedicated routing?


To use the dedicated routing, simply pin assign the signal to the appropriate pin and ensure that the "Use Global CLK/GSR/OE" options are enabled in the Fit Process Properties.

The tools will automatically use the dedicated routing as long as there is no logic between the pin and the dedicated resource (with the exception of an inverter).

For example, a register that is reset by "resetpin and counter(6)" will not use the dedicated routing because there is no logic available between the GSR pin and the reset port of the register.

However, a register that is reset by "not resetpin" will use the dedicated routing.

To verify that the dedicated logic was used, check the fitter report.

The first page should include a section that looks like the following:

** Global Control Resources **

Signal 'fclk' mapped onto global clock net GCK1.

Global output enable net(s) unused.

Global set/reset net(s) unused.

If the dedicated resource is being used, it will be listed above.

You can internally generate clocks,resets, and output enables and put them on global routing using an alternate method. See (Xilinx Answer 5572).

AR# 10453
日期 09/19/2017
状态 Active
Type 综合文章
  • 9500
  • 9500XL
  • 9500XL IQ
  • More
  • 9500XL XA
  • 9500XV
  • CoolRunner XPLA3
  • CoolRunner-II
  • CoolRunner-II XA
  • Less