General Description: Rather than appearing as a CORE Generator module underneath an HDL source file, the CORE Generator icon appears as a top-level source.
The most common reason for this is that the calling HDL source is using one of the following black box attributes (VHDL examples shown):
-- FPGA Express Black Box declaration attribute fpga_dont_touch: string; attribute fpga_dont_touch of mult8x8s: component is "true"; -- XST black box declaration attribute box_type : string; attribute box_type of mult8x8s: component is "black_box";
These attributes are no longer necessary for correct processing of COREGen components through their respective synthesis tools in Foundation ISE, so they may be safely removed. Once these are removed and the source file saved, the COREGen icon will appear under the calling HDL source in the hierarchy view.