When a simultaneous read and write to the same location occurs, the write operation always succeeds. However, the read operation is not guaranteed to work.
When behavioral simulation is run for CORE Generator dual-port block memory, the read operation may report meaningful data on the output port. However, this is incorrect and should not be considered valid data.
For Virtex, Spartan-II, and Virtex-E devices, do not perform a simultaneous read and write to the same location in simulation or in the actual device operation. If this condition cannot be avoided, consider the data on the read port to be invalid.
For Virtex-II and Virtex-II Pro devices, refer to Chapter 2 of the Virtex-II Platform FPGA User Guide "Using Block SelectRAM Memory" (see the "Conflict Resolution" section).
The Virtex-II Hardware User Guide is located at: