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4.1i CPLD CPLDFit - Pin assignments (pin locks) are not being recognized
Keywords: XC9500, CoolRunner XPLA3, pin lock, pin assignment
The fitter appears to be ignoring my pin locks; what am I doing wrong?
1 Check your log (console window) to see if any warnings scrolled off the window that explain why pin locks were not used.
In the implementation options, under the Basic tab, ensure that you have "Use Location Constraints" set to "Always".
If you have this set to "Try," the software will take the pin assignments into consideration when fitting the design, but may move pins around for a better fit.
2 Make sure that you are using the appropriate bus delimiters and have used the proper syntax.
If you have a bus in VHDL declared as:
datain : in std_logic_vector(1 downto 0);
the proper pin-locking notation for the UCF is:
net datain<0> loc = p5;
net datain<1> loc = p6;
This may vary from one synthesis vendor to another. (The above example is appropriate for XST.)
For more details on how to perform pin locking, please see (Xilinx Answer 2719).