AR# 10573

3.1i XST - VERILOG synthesis: XST hangs at 50% when synthesizing a Verilog file.

描述

Keywords: hang, Verilog, CPLD

Urgency: Standard

General Description:
XST has been seen to hang at 50% when synthesizing for CPLDs.

解决方案

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 6.
AR# 10573
日期 08/19/2002
状态 Archive
Type 综合文章