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AR# 1061

SYNPLIFY: How is the top level module or entity/architecture determined?


Keywords: Synplify, VHDL, Verilog

Urgencey: Standard

General Description:
How does Synplify determine the top level module or entity/architecture?


For synthesis, Synplify scans the input source files from top to bottom of
the source file list. For Verilog, the top level module is the last module it
finds that is not instantiated somewhere in the design. For VHDL, it is the
last architecture of the last entity that it finds. Therefore it is best for both
languages to put your to level as the last object in the last design file in
your list of input source files.
AR# 1061
日期 04/20/2007
状态 Archive
Type 综合文章