AR# 1061: SYNPLIFY: How is the top level module or entity/architecture determined?
AR# 1061
SYNPLIFY: How is the top level module or entity/architecture determined?
描述
Keywords: Synplify, VHDL, Verilog
Urgencey: Standard
General Description: How does Synplify determine the top level module or entity/architecture?
解决方案
For synthesis, Synplify scans the input source files from top to bottom of the source file list. For Verilog, the top level module is the last module it finds that is not instantiated somewhere in the design. For VHDL, it is the last architecture of the last entity that it finds. Therefore it is best for both languages to put your to level as the last object in the last design file in your list of input source files.