AR# 10628


FPGA Compiler II - Re-timing (register balancing) does not appear to offer any improvement.


Keywords: register, balance, retime, re-time, FPGA, Compiler II

Urgency: Standard

General Description:
What can I do if the re-timing function does not appear to offer any improvement in
FPGA Compiler II?


1. Synthesize the design without I/O pads inserted.
2. Re-time the design during this synthesis run.
3. Read the resulting EDIF back into FPGA Compiler II.
4. Re-synthesize and write out the EDIF WITH I/O inserted.
AR# 10628
日期 04/20/2007
状态 Archive
Type 综合文章
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