AR# 10631


3.5 FPGA Express - FPGA Express is not implementing the SRL16 properly.


Keywords: SRL, 16, SRL16, shift, 3.5

Urgency: Hot

General Description:
Express 3.5 (build will implement shift registers incorrectly in Virtex/-E/-II and
Spartan-II devices. Regardless of the length of the shift register you have coded, it utilizes
the full 16-clock-cycle delays of the inferred SRL16 component, even if your code has
been written to infer a smaller shift register.



An updated version of FPGA Express 3.5 is now available to correct this problem.
This update is build and may be downloaded from:

The file is called FPGAExp35.exe and the "Posted" date is 1/5/2001.

Please be advised that this update fixes this problem when synthesizing the
design through the FPGA Express, Foundation or ISE GUI. However, the
problem still exists when FPGA Express is run through the FE_Shell scripting tool.
The scripting problem will be corrected in a future build of FPGA Express.

To determine if you have the updated version or not, open FPGA Express by

Start -> Programs -> Xilinx Foundation Series (ISE) -> Accessories -> FPGA Express.
Select Help -> About FPGA Express.

The build number for the corrected version of software is

To install the updated version, follow the installation instructions provided in the
Readme file on the Service Pack web page mentioned above. You should
reinstall the entire Service Pack as detailed in the Readme, not just the FPGA
Express portion.

If you need to use fe_shell for scripting, then you will need to instantiate the SRL
length that you want; to get a fixed-length shift register, drive the A3 through A0
inputs with static values. The length of the shift register can vary from 1 bit to
16 bits, as determined through use of the following formula:

Length = (8*A3) +(4*A2) + (2*A1) + A0 +1

If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones
(1111), it is 16 bits long.

VHDL Example:

library ieee;
use ieee.std_logic_1164.all;

entity srl_instantiation is
port (D : in STD_LOGIC;
Q : out STD_LOGIC);
end entity;

architecture srl_arch of srl_instantiation is

component SRL16
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;

signal A : std_logic_vector (3 downto 0);


A <= "0100"; -- A 5 clock cycle shift

u1 : SRL16 port map
(D => D,
A0 => A(0),
A1 => A(1),
A2 => A(2),
A3 => A(3),
Q => Q);

end architecture;


Verilog Example:

module srl_instantiation (D, CLK, Q);
input D, CLK;
output Q;

wire [3:0] A;

assign A=4'b0100; // A 5 clock cycle shift

SRL16 u1 (.D(D), .CLK(CLK), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .Q(Q));


AR# 10631
日期 08/21/2002
状态 Archive
Type 综合文章
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