General Description: How do I implement the Readback block in FPGA Express for 4000/Spartan families?
解决方案
1
VHDL Example:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity use_readback is port (trig : in std_logic; rip : out std_logic; data: out std_logic; clk, d_in: in std_logic; read_clk : in std_logic; q: out std_logic); end use_readback;
architecture xilinx of use_readback is
component READBACK port (CLK, TRIG: in std_logic; DATA: out std_logic; RIP: out std_logic); end component;
begin
u1: READBACK port map (CLK => read_clk, TRIG => trig, DATA => data, RIP => rip);
-- Sample User Code My_D_Reg: process (clk) begin if (clk'event and clk='1') then q <= d_in; end if; end process; -- End My_D_Reg