描述

解决方案

The calculation for External Setup time for pad-to-register paths:

Tsu(ext) = T(data_path) + Tsu(int) - T(clock_path)
T(data_path) = maximum data path delay
Tsu(int) = setup time of an internal register
T(clock_path) = minimum clock path delay

The calculation for the external Hold time for pad-to-register paths:

Th(ext) = T(clock_path) + Th(int) - T(data_path)
T(data_path) = minimum data path delay
Th(int) = hold time of an internal register
T(clock_path) = maximum clock path delay
An example of the External Setup and Hold times is illustrated in the following figure:

Figure 1 - Example Setup & Hold Times

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf