We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10680

Exemplar 1999 - How do I prevent a signal from being optimized? ("don't touch"/"keep")


General Description:

I wish to prevent Exemplar from optimizing logic in certain designs (as when I create a ring oscillator or an asynchronous delay). What syntax can I use to prevent Exemplar from optimizing this logic?


While Xilinx strongly recommends that asynchronous delays not be placed into designs, and ring oscillators are often unpredictable in FPGAs, the syntax for preventing optimization in Exemplar is as follows:

library ieee;

use ieee.std_logic_1164.all;

entity test is port(

a: in std_logic;

y : out std_logic);

attribute preserve_signal : boolean;

end test;

architecture beh of test is

signal b : std_logic;

attribute preserve_signal of b : signal is true;


b <= not a;

y <= not b;

end beh;
AR# 10680
日期 05/10/2012
状态 Archive
Type 综合文章