AR# 10698


3.1i COREGEN - Multiply Generator can not be generated when an input width of "1" is selected for port A.


Keywords: CORE Generator, multiply, generator, multiplier, Coregen

Urgency: Standard

General Description:
When generating CORE Generator Multiply Generator v2_0, I encounter the
following messages:

Xilinx Core Generator - An Error has Occurred.
Sim has a problem implementing the selected core. Implementation
netlist will not be generated.

ERROR: Sim Generator: Failure of Sim to implement customization parameters core mult_1

ERROR: Core mult_1 did not generate EDIF implementation netlist. (.EDN) file.

WARNING: Warnings and/or errors encountered while generating mult_1 (Multiplier 2.0)
All output products requested may not have been generated.

ERROR: Elaboration failure for core Multiplier.

ERROR: Elaboration of core Multiplier failed.


This problem occurs when an input width of "1" is selected for port A. If applicable,
generate a core with a width of "2" or greater, and tie the unnecessary upper bits
to logic "1," or to the appropriate level.

This problem is scheduled to be fixed in the next IP update, due out in March, 2001.
AR# 10698
日期 08/23/2002
状态 Archive
Type 综合文章
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