You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
3.5 FPGA Express - FPGA Express creates bad logic under certain conditions
FPGA Express version 3.5.0 contains a bug which may create bad logic under the
1. The design is coded in Verilog;
2. The design includes a Finite State Machine with a state encoded as 0;
3. The user chooses to invoke the "Advanced HDL Compiler (Presto)" option.
The "Presto" compiler is not the default compiler. The "Compatible (HDLC)"
compiler operates correctly.
To solve this problem, use one-hot state encoding for each Verilog state machine. You
must write state encoding directly into the RTL code.
Turn off the new "Presto" compiler.
From within Foundation ISE:
1. Right-click on the "Synthesis" process.
2. Select "Properties..."
3. De-select "Enable Presto HDL Compiler."
From within FPGA Express stand-alone:
1. Select the Synthesis pull-down menu.
2. Select "Options."
3. Select the Project tab.
4. Select "Compatible HDL Compiler - HDLC."
Foundation (Aldec version):
The Presto compiler option is not selectable from within Foundation.