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AR# 1073

PAR: "Number of GCLKS 5 out of 4" with Virtex Synplify netlist


Keywords: Synplify, Virtex, Par

Urgency: Standard

General Description:
Synplify will insert 4 global clock buffers on the signals with
the highest fanout. However, if the design also contains
a BUFGDLL, then PAR will error with a the number or GCLKS
exceeding the available resources.


The problem exists with Synplify. The BUFGDLL cell is not counted as a
BUFG resource and Synplify inserts another 4 BUFG or BUFGP cells violating
the resource limit of 4 for Virtex.

Please see (Xilinx Solution 4084) on how to disable BUFG insertion.

AR# 1073
日期 03/29/2000
状态 Archive
Type 综合文章