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AR# 1078

ModelSim (MXE, SE, PE) - How do I run a functional (behavioral) simulation with ModelSim stand-alone? (VHDL, Verilog)

Description

Keywords: ModelSim, XE, MXE, PE, SE, Vsim, behavioral, functional, rtl, simulation

Urgency: Standard

General Description:
How do I run a functional simulation with ModelSim?

For information on running a back-annotated (timing) simulation using ModelSim stand-alone, please see (Xilinx Answer 10177).

解决方案

Running Simulation from Project Navigator (VHDL or Verilog)
When running a simulation from ProjNav, ProjNav will automatically run the behavioral simulation. Select the Testbench in the Sources Window in ProjNav, then run the Simulate Behavioral Model process in the Processes Window.

For additional information on how to run simulation from ProjNav, please see (Xilinx Answer 18216).

Verilog - Running MTI Stand-alone
1. If you have not compiled the Xilinx Simulation Libraries, please see (Xilinx Answer 15338) for information on how to compile the libraries.

2. Compile the "glbl.v" module, the source files, and the testbench. For example:
vlog $env(XILINX)/verilog/src/glbl.v <source1>.v <source2).v ... <testbench>.v

For more information about the "glbl.v" module, please see (Xilinx Answer 6537).

3. Load the design in ModelSim and use the -L switch to point to the libraries being used in the design. The "glbl" needs to be loaded as well.
vsim -t ps -L unisims_ver -L xilinxcorelib_ver work.<testbench> work.glbl

NOTE: The "glbl.v" automatically pulses Global Set/Reset (GSR) for the first 100 ns of the simulation. See (Xilinx Answer 6537) for more information.

VHDL - Running MTI Stand-alone
1. If you have not compiled the Xilinx Simulation Libraries, please see (Xilinx Answer 15338) for information on how to compile the libraries.

2. Compile the source files and the testbench. For example:
vcom -93 <source1>.vhd <source1>.vhd ... testbench.vhd

3. Load the design:
vsim -t 1ps work.<testbench>

NOTE: In a back-annotated (timing) simulation, the Global Set/Reset (GSR) will automatically be pulsed for the first 100 ns of simulation. To prepare for this, it would be good to reserve the first 100 ns in the testbench for reseting the design. For additional information about GSR in simulation, please refer to (Xilinx Answer 5009).
AR# 1078
创建日期 06/27/1996
Last Updated 11/24/2003
状态 Active
Type 综合文章