AR# 10793


3.1i CPLD XC9500XL Hitop - Clock-enable emulation produces incorrect logic


Keywords: CPLD, CE, negative logic, 9500XL, Hitop, clock enable

Urgency: Hot

General Description:
When a macrocell implements negated logic (i.e., /q := ...) and uses clock-enable at the same time, the fitter then gets the logic wrong for "q" when/if it emulates the clock-enable. This is shown in timing simulation as well as in device operation.



This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 8.

For more information on this bug, including a work-around for users without Service Pack 8, please see Resolution 2.


There is a logic corruption that occurs under the following circumstances:

1. Negative logic is used for the register equation, and
2. The CE equation for the register requires more than one P-term.

The problem is in the optimization of the CE pin logic for the register. This optimization is done to prevent the need for another macrocell to implement the multi-P-term CE logic; this keeps the CE pin from becoming a timing hindrance.

The optimization currently causes an improper inversion.


/q := x
q.ce = ce

is emulated as:

/q := x*ce + q*/ce

It should be:

/q := x*ce + /q*/ce

The work-around is to prevent CE optimization. To do this, include the following line in the UCF file:


where sig_EN is the name of the net connected to the clock-enable pin of the register.
AR# 10793
日期 08/23/2002
状态 Archive
Type 综合文章
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