General Description: When a macrocell implements negated logic (i.e., /q := ...) and uses clock-enable at the same time, the fitter then gets the logic wrong for "q" when/if it emulates the clock-enable. This is shown in timing simulation as well as in device operation.
For more information on this bug, including a work-around for users without Service Pack 8, please see Resolution 2.
There is a logic corruption that occurs under the following circumstances:
1. Negative logic is used for the register equation, and 2. The CE equation for the register requires more than one P-term.
The problem is in the optimization of the CE pin logic for the register. This optimization is done to prevent the need for another macrocell to implement the multi-P-term CE logic; this keeps the CE pin from becoming a timing hindrance.
The optimization currently causes an improper inversion.
/q := x q.ce = ce
is emulated as:
/q := x*ce + q*/ce
It should be:
/q := x*ce + /q*/ce
The work-around is to prevent CE optimization. To do this, include the following line in the UCF file:
NET sig_EN REG=CE;
where sig_EN is the name of the net connected to the clock-enable pin of the register.