# AR# 10835

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## 描述

Keywords: Virtex-5, Virtex-4, Spartan-3, Spartan-3E, Virtex-II Pro, I/O, input, output, 5V, tolerant, 3.3V, Virtex-II Pro, Virtex-E, Virtex-II

Are Xilinx FPGA I/Os 5V-tolerant? For example, can I drive Virtex-II I/Os with a voltage higher than the VIH of the I/O standard?

## 解决方案

#### 1

Xilinx Virtex-E, Virtex-II, Spartan-3, Spartan-3E, Virtex-II Pro, Virtex-4 and Virtex-5 I/Os are not 5V-tolerant without the addition of an external current-limiting resistor. Each of these FPGA I/O contains a pair of clamp diodes that connect to VCCO and GND, as shown in the appropriate data sheets.

However, for LVCMOS/LVTTL I/O standards, you can work around this problem by using a resistor in series to limit the current into the clamp diode. This works only for a higher voltage that is driving Virtex-II input. It does not work for a Virtex-II output or bidirectional signal because the resulting VOH will be lower than the specification of the other device.

The following is a calculation example given the following:

- The forward-bias voltage of the clamp diode is 0.5 V.
- The limit that any I/O pin can be overdriven above or below the limits of GND and VCCO is 10 mA.

Assuming that you want to drive 5V from device "X" to the LVCMOS33 input in Virtex-II:

- The VCCO min. for the LVCMOS33 is 3.0 V.
- The VOH max. for the LVCMOS5 is 5.25.

This means that the diode will be forward-biased at a voltage of 3.0 +0.5 = 3.5 or higher:

- Your maximum voltage difference will be 5.25 - 3.5 = 1.75 V.
- To limit the current to 10 mA, you need a resistor(R) of 1.75/10 mA = 175 ohm.

NOTES:
1. Follow the simultaneous switching output (SSO) guideline. Refer to the "Virtex-II Platform FPGA User Guide" at:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/User+Guides/FPGA+Device+Families/Virtex-II/&iLanguageID=1

Select Design Considerations -> Using Single-Ended Select I/O Ultra Resources -> Design Considerations -> Simultaneous Switching Output (SSO) Guidelines. Table 2-37 lists the maximum number of simultaneously switching outputs per Power/Ground pin pair.

2. The minimum VCCO is for worst-case calculation.

3. Maintain a stable, clean, and properly bypassed VCCO at all times.

4. Place the resistor closer to the driver for better signal integrity.

5. Perform IBIS simulation to verify the result.

6. The clamp diodes are always present (programmed, unprogrammed, during configuration), and there is never a need to add external clamp diodes in the event that the Virtex-II is unprogrammed and has 5V signals driving the pins.

#### 2

AR# 10835

Type 综合文章
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