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General description:
How do I implement a Synchronous Reset in VHDL in Synplicity or Exemplar?
VHDL
No special attributes are necessary to implement a synchronous reset. Your VHDL code should look as follows:
process (CLK)
begin
if (CLK'event and CLK='1') then
if (RESET='1') then
COUNT <= "00000000";
else
COUNT <= COUNT + 1;
end if;
end if;
end process;
Verilog
No special attributes are necessary to implement a synchronous reset. Your Verilog code should look as follows:
always @(posedge CLK)
begin
if (RESET)
COUNT = 0;
else
COUNT = COUNT + 1;
end;
AR# 10840 | |
---|---|
日期 | 05/14/2014 |
状态 | Archive |
Type | 综合文章 |