General Description: Problem 1 When running behavioral simulation for Single Port Block Memory v3_0, I encounter an error/warning from the simulator regarding an incorrect number of parameters in the port list.
Problem 2 When running behavioral simulation for Dual Port Block Memory v3_0, I encounter "xxxx" on the output port when trying to access the invalid address location.
Problem 3 When reading the data sheet for Encoder_8b10b v1_0, the title and the section headers are illegible.
Problem Source The original 32i_ip_update2.zip and 32i_ip_update2.tar.gz contain duplicate files. The file names are the same, but one is written in lower-case letters and the other in upper-case. The lower-case file is correct, and the capitalized file is not.
1. Remove the files below from your current Xilinx installation. Your Xilinx 3.1i software is installed in <XILINX>. You may have only one file in each directory (either in upper- or lower-case), but it is necessary to delete both of them.
4. If you plan to perform behavioral simulation using the Verilog models provided in <XILINX>\verilog\src\XilinxCoreLib, you may need to re-compile the following, depending upon the simulator you are using:
blkmemdp_v3_0.v and blkmemsp_v3_0.v
Using your Verilog simulator, you can either re-compile all the files in the XilinxCoreLib directory, or just the two files listed above if you have already compiled the other files.
For UNIX systems:
Both the upper-case and lower-case files will be saved; therefore, it is not necessary to install the newer update. Simply delete the incorrect files from appropriate directories: