We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10879

3.1i Virtex-II MAP - Packer changed to prevent DP/SP RAM combination in a Virtex-II slice.


Keywords: DP RAM, SP RAM, combined, 16x1

Urgency: Standard

General Description:
The packer has been changed to make the combination of a 16x1 SP RAM and the dual-port
half of a 16x1DP RAM in the same slice illegal. (This had been causing placer errors, and was
only useful when the SP is really half of a RAM16x2S; in this case, a 16x2 symbol should be used.)


This change is available in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the change is 3.1i Service Pack 7.
AR# 10879
日期 08/19/2002
状态 Archive
Type 综合文章