AR# 1089: VERILOG-XL: Specifying multiple libraries in a Verilog simulation
AR# 1089
VERILOG-XL: Specifying multiple libraries in a Verilog simulation
描述
Keywords: multiple verilog libraries simulation
Urgency: standard
General Description: Multiple libraries can be specified for a Verilog simulation using the `uselib directive, but the procedure in the Cadence Openbook online documentation needs some clarification.
解决方案
1
To declare multiple libraries that are to be searched with a single `uselib directive.
For readability, each macro may be defined in terms of a `define text macro:
All libraries you wish to specify must be on the same line. Note the use of the "\" line continuation character at the end of the first line, which tells the interpreter to concatenate the next line with the previous one.
2
You can also do this in command line mode using the -y option as follows:
Say you have libraries in directories lib1 and lib2, and the extensions in these libraries are ".v" and ".vpd" respectively. To specify the two libraries on the Verilog command line, you would invoke Verilog-XL in the following manner: