AR# 10902

3.1i SP7 - 3.1i Service Pack 7 update

描述

Keywords: Service, Pack, 3.1i, update, 3.3.07i,

Urgency: Standard

General Description:
This answer contains a complete list of all changes included in the M3.1i Service
Pack 7 Update.

解决方案

The Service Pack Update Page is located at:
http://support.xilinx.com/support/techsup/sw_updates/

The following issues are addressed by the 3.1i Service Pack 7 Update:

{SP} Denotes Which Service Pack Contained This Fix

BITGEN

{SP7} (Xilinx Answer #10877): 3.1i BitGen - Incorrect check of
keypasses in Virtex-II key files.

{SP7} (Xilinx Answer #10590): 3.3i Virtex-II BitGen - BitGen may
create incorrect bit files for Virtex-II devices.

{SP5} (Xilinx Answer #10401): 3.1i BitGen - TDO2 programmable inverter
equations are wrong (TDO2 is wrong polarity).

{SP5} (Xilinx Answer #10402): 3.1i BitGen - IOB FF worked using 2.1i
BitGen but is stuck in reset using 3.1i

{SP4} (Xilinx Answer #9922): 3.1i BitGen - I/O's are not 5V-tolerant for
Virtex architectures (Vcco rail is rising above 3.3V).

{SP2} (Xilinx Answer #9705): 3.1i BitGen - BitGen will create a debug
bitstream with the option DebugBitstream:No.

{SP2} (Xilinx Answer #9707): 3.1i BitGen - Feedback 2x memory cell is not
set correctly when using DLLIOB for feedback.

{SP2} (Xilinx Answer #9706): 3.1i BitGen - LVPECL inputs on top edge of
Virtex-E devices are not configured properly.

{SP2} (Xilinx Answer #9431): 3.1i BitGen - ERROR: 145 - Pin ... is a
persistent pin, but a component ..."

{SP1} (Xilinx Answer #9429): 3.1i Virtex-E BitGen - Greater than a 0.3 ns
difference seen between the input clock of a DLL and the feedback path.

CABLES

{SP1} (Xilinx Answer #8777): 3.1i MultiLINX Cable - Issues with Windows 98 SE,
Windows 2000, and USB.

CHIP VIEWER

{SP6} (Xilinx Answer #10587): 3.1i CPLD ChipViewer - Hangs on "Resizing Layout" when
targeting an XC95288XL-6 device.

{SP4} (Xilinx Answer #9382): 3.1i CPLD ChipViewer - ChipViewer fails to start ("Out of
environment space").

{SP4} (Xilinx Answer #9901): 3.1i ChipViewer - Timing analyzer results are not being
displayed.

CONSTRAINTS EDITOR

{SP2} (Xilinx Answer #8682): 3.1i Constraints Editor - No IO Standard available for clock signals.

CPLD

{SP6} (Xilinx Answer #10585): 3.1i CPLD Hprep6 - XC9500 device operation does not match
simulation.

{SP3} (Xilinx Answer #9824): 3.1i CPLD HPrep6 - When will JEDEC support be enabled for
the XC9500XV Family?

{SP2} (Xilinx Answer #9731): 3.1i CPLD TAEngine - 95288XL-7 speed grade displays -10
timing values.

{SP1} (Xilinx Answer #9004): 3.1i CPLD 9500XV Hitop - Only LVTTL bi-directional signals
are allowed.

{SP1} (Xilinx Answer #4100): 3.1i XC9500 Family Hitop - PROHIBIT property does not
exclude pins from the "Programmable Ground Pins" option.

{SP1} (Xilinx Answer #9658): 3.1i CPLD TAEngine - Fails to expand wildcards [*] when
processing timing constraints.

DESIGN MANAGER

{SP1} (Xilinx Answer #9606): 3.1i Design Manager - Post-Layout Timing Report should
should not be automatically generated after executing MPPR.

ECS

{SP4} (Xilinx Answer #10280): 3.1i Foundation ISE - ECS property on CLKDLL,
CLKDLLE, CLKDLLHF and DCM does not work.

FLOORPLANNER

{SP5} (Xilinx Answer #9934): 3.1i Floorplanner - Pin LOC gets changed when it
moves from the Placement window to the Floorplan window.

{SP3} (Xilinx Answer #10014): 3.1i Floorplanner - Crashes/Core Dumps when
loading design.

{SP2} (Xilinx Answer #9171): 3.1i Floorplanner - Constraints are not
being implemented correctly.

{SP2} (Xilinx Answer #6240): 3.1i Floorplanner - Write AG constraints in
UCF to *not* include lower-level instances.

{SP2} (Xilinx Answer #8136): 3.1i Virtex-E Floorplanner - Secondary DLL
does not appear in the Floorplanner.

{SP1} (Xilinx Answer #2740): 3.1i Floorplanner - Pin constraints in UCF
file show up incorrectly in the Floorplanner.

{SP1} (Xilinx Answer #9033): 3.1i Floorplanner - Error Portability 3:
application has run out of memory or Segmentation Fault.

FPGA EDITOR

{SP7} (Xilinx Answer #10298) : 3.3i FPGA Editor - Editing an IOB block gives
the following error : FATAL_ERROR:Ncd:bascmtform.c:161:1.4 - Unable to
find button PCI33_5 on primative IOATTRBOX in cell IOB.

{SP4} (Xilinx Answer #10015): 3.1i FPGA Editor - Crashes when saving NCD
after modifying design.

{SP4} (Xilinx Answer #9975): 3.1i FPGA Editor - Crashes when trying to
implement the ILA features.

{SP1} (Xilinx Answer #9357): 3.1i Virtex FPGA Editor - Adding a pin to
GLOBAL_LOGIC signal leads to crash.

{SP1} (Xilinx Answer #8697): 3.1i FPGA Editor - Trace Summary selects the
wrong constraint.

FPGA Express

{SP6} (Xilinx Answer #9464): 3.4 FPGA Express - Verilog concatenation with an
addition synthesized incorrect logic.

{SP6} (Xilinx Answer #7242): 3.4 FPGA Express - FPGA Express inserts ILD for
an ILDX_1 instantiation.

HARDWARE DEBUGGER

{SP1} (Xilinx Answer #9630): 3.1i Hardware Debugger - Internal DCE
Threads problem while running on HP platform.

INSTALL

{SP1} (Xilinx Answer #9672): 3.1i Service Pack Install - Canceling the
Service Pack Install gives message: "Install Completed Successfully"

JTAG PROGRAMMER

{SP6} (Xilinx Answer #9452): 3.1i JTAG Programmer - ERROR: JTag - Illegal character ?
(/37777777637) at line 633 in BSDL description.

{SP5} (Xilinx Answer #10405): 3.1i XC18V00 JTAG Programmer - added
NORMRST between program and verify for 18V01, 18V512 18V256

{SP4} (Xilinx Answer #10252): 3.1i XC18v00 JTAG Programmer - "Verify"
option disabled in program options dialog.

{SP4} (Xilinx Answer #10059): 3.1 JTAG Programmer - MultiLINX cable does
not consistently program 18v04 for Parallel Mode.

{SP4} (Xilinx Answer #10253): 3.1i XC18v00 JTAG Programmer - SVF for Get
USERCODE fails with wrong value.

{SP4} (Xilinx Answer #9862): 3.1i XC18v00 JTAG Programmer - SVF verify
unsuccessful.

{SP4} (Xilinx Answer #10005): 3.1i XC18v00 JTAG Programmer - missing the
XC18V256 VQ44 part.

{SP3} (Xilinx Answer #10018): 3.1i XC1800 JTAG Programmer - PROM verify
voltage margin raised.

{SP2} (Xilinx Answer #9790): 3.1i JTAG Programmer - HP-UX crashes or does
not connect with the XChecker cable

{SP2} (Xilinx Answer #9646): 3.1i JTAG Programmer - When write protect is
selected, the checksum will mismatch.

{SP2} (Xilinx Answer #9791): 3.1i Virtex JTAG Programmer - SVF status
check on DONE pin fails.

{SP1} (Xilinx Answer #9647): 3.1i JTAG Programmer - Dr. Watson error
while trying to generate SVF program device.

{SP1} (Xilinx Answer #9645): 3.1i XC1800 JTAG Programmer - XC1804 remains
in ISP mode after operation has finished.

{SP1} (Xilinx Answer #9644): 3.1i XC9500 JTAG Programmer - On programming
failure, Xilinx software does not erase the CPLD.

{SP1} (Xilinx Answer #8224): 3.1i XC18V00 JTAG Programmer - JTAG
Programmer 3.1i does not support XC18V00 SVF generation.

MAP

{SP7} (Xilinx Answer #10734): 3.1i Virtex MAP - FDS and FDRS are incorrectly packed
into the same slice.

{SP7} (Xilinx Answer #10635): 3.1i SP6 Virtex/Spartan-II MAP - Crash during unrelated
packing on PC only.

{SP7} (Xilinx Answer #10890): 3.1i Virtex-II MAP - Invalid pack errors may occur
if RLOCs are used with RAM64x2 or RAM128x1.

{SP7} (Xilinx Answer #10544): 3.1i Virtex-II MAP - "ERROR:Portability:3 - This
Xilinx application has run out of memory..."

{SP7} (Xilinx Answer #10879): 3.1i Virtex-II MAP - Packer changed to prevent
DP/SP RAM combination in a Virtex-II slice.

{SP7} (Xilinx Answer #10321): 3.3i MAP - XC2S30-pq208: no connects in data sheet:
p13, p38, p118, p143 are being reported as Vccint in pad report.

{SP6} (Xilinx Answer #10575): 3.1i Virtex MAP - Combined BLKRAM and slice-based area-
groups are not translated correctly to PCF.

{SP6} (Xilinx Answer #9940): 3.1i Virtex-E MAP - MAP runs out of memory while loading
NGD under Windows2000.

{SP5} (Xilinx Answer #10213): 3.1i MAP - FATAL_ERROR: MapHelpers:
mhcconstimp.c:162:1.7.20.1 - resolveSiteType() ...

{SP4} (Xilinx Answer #10254): 3.1i Virtex MAP - A bad NGM file is
produced by MAP, affecting simulation results.

{SP4} (Xilinx Answer #9973): 3.1i Virtex MAP - ERROR:Pack:679 - Unable to
obey design constraints.

{SP4} (Xilinx Answer #10026): 3.1i Virtex MAP - RAM/SRL16E packed with
latch results in bad clock inversion.

{SP3} (Xilinx Answer #10027): 3.1i Virtex MAP - ERROR:Pack:679 - Unable
to obey design constraints ...

{SP3} (Xilinx Answer #10028): 3.1i Virtex MAP - ERROR:Pack:679 - Unable
to obey design constraints ...

{SP2} (Xilinx Answer #9536): 3.1i Virtex-E MAP - Crash after "Running
Directed Packing..." due to incorrect MUXF5 trimming.

{SP2} (Xilinx Answer #9534): 3.1i Virtex-E MAP - FATAL_ERROR:
Pack:pksvrsliceusg.c:508:1.20.10.1 Never found the LUT address signal

{SP2} (Xilinx Answer #9723): 3.1i Virtex MAP - RPM macro's carry chain
alignment disrupted by map trimming.

{SP2} (Xilinx Answer #9053): 3.1i Virtex MAP - Problems with implementation
and back-annotation of FDCP with INIT=R.

{SP1} (Xilinx Answer #9591): 3.1i Virtex MAP - Core dump (bus error) during
modular design assembly phase.

{SP1} (Xilinx Answer #9344): 3.1i Virtex MAP - Some eligible registers are not
being packed into IOBs.

{SP1} (Xilinx Answer #9077): 3.1i Virtex MAP - ERROR:DesignRules:368 -
Netcheck: Sourceless. Net $3I2/..... has no source.

NCDesign

{SP5} (Xilinx Answer #10156): 3.1i Virtex-E NCDesign - Software will not
support IBUFG_LVDS inputs for XCV405E.

NGD2VER

{SP5} (Xilinx Answer #10302): 3.1i Virtex-E NGD2VER - time_sim.vhd file
contains generic FACTORY_JF for X_CLKDLL2 module which is not in SimPrim model.

NGDANNO

{SP7} (Xilinx Answer #10904): 3.3i NGDAnno - Running NGDAnno with NGM
file creates large delay on CLK port.

{SP7} (Xilinx Answer #10903): MTI Timing simulation - Possible setup violations
are caused by NGDAnno not annotating delays between SRL16 and a flip-flop
that are in the same slice.

NGDBUILD

{SP6} (Xilinx Answer #9573): 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4
MAX ELEMENT COUNT EXCEEDED.

{SP6} (Xilinx Answer #10223): 3.1i NGDBuild - XML Parser environment is incorrectly
set up, preventing it from finding its text transcoding files.

{SP2} (Xilinx Answer #9380): 3.1i NGDBuild - ERROR:NgdBuild:393 - Could not find INST(S)
'GRP0' in design 'top'...

{SP1} (Xilinx Answer #9573): 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4
MAX ELEMENT COUNT EXCEEDED.

PACKAGE FILES

{SP5} (Xilinx Answer #10393): 3.1i Virtex-E Package Files - The BG560
package is now available for XCV400E and XCV600E.

{SP4} (Xilinx Answer #10259): 3.1i Virtex-II Package Files - New Virtex-II
package files are included in 3.1i Service Pack 4.

{SP3} (Xilinx Answer #10030): 3.1i XC4000XL/XC4000XLA Package Files -
Missing pins result in incomplete .pad file from PAR.

{SP3} (Xilinx Answer #10031): 3.1i XC4000XLA Package Files - The
XC4085XLA BG352 package has bad pin out.

{SP3} (Xilinx Answer #10032): 3.1i Virtex Package Files - XV150 FG456
missing VCC pin J7 leading to incomplete .pad file.

{SP3} (Xilinx Answer #10037): 3.1i Spartan-II Package Files - x2s15 TQ144
package missing N.C. pins leading to incomplete .pad file.

{SP3} (Xilinx Answer #10050): 3.1i Spartan Package Files - Packages are
missing some no connect pins, affecting .pad report.

{SP3} (Xilinx Answer #10051): 3.1i XC4000E Package Files - Several
package files are missing pins, affecting the .pad file.

{SP3} (Xilinx Answer #10052): 3.1i Virtex Package Files - The Virtex
CB228 package files are missing pins, affecting the .pad report.

{SP2} (Xilinx Answer #9711): 3.1i Package Files - P39 in XC2S50 PQ208
package is listed as VCCINT instead of NC.

{SP2} (Xilinx Answer #9710): 3.1i Spartan-II Package Files - X2S200 FG456
and BG352 package files are missing VCCINT pins.

{SP2} (Xilinx Answer #3149): 3.1i Package Files - Spartan XCS10 TQ144
does not have the TMS pin bonded.

PAR

{SP7} (Xilinx Answer #10872): 3.1i Virtex-II PAR - PAR hangs while routing
PWR/GND nets in a Virtex-II design.

{SP7} (Xilinx Answer #10705): 3.1i Virtex-II PAR - PAR hangs while routing
PWR/GND nets in a Virtex-II design.

{SP7} (Xilinx Answer #10870): 3.1i Virtex-II PAR - Placer not honoring LOC
constraints on slices.

{SP7} (Xilinx Answer #10868): 3.1i Virtex-II - PAR runs out of memory on
Virtex-II designs with area groups.

{SP7} (Xilinx Answer #10505): 3.1i Virtex-II PAR - Placer unable to handle
certain legal DPRAM configurations.

{SP6} (Xilinx Answer #10561): 3.1i Virtex-E PAR - Placer rejects placement of slices
containing F5/F6 MUX.

{SP6} (Xilinx Answer #10566): 3.1i Virtex PAR - Placer places two signals on one SIGPIN.

{SP5} (Xilinx Answer #10392): 3.1i Virtex PAR - FATAL_ERROR:Route:basrtsanity.c:168:1.7.28.1
- Process will terminate.

{SP5} (Xilinx Answer #10284): 3.1i Virtex PAR - FATAL_ERROR: Route:
basrtalg.c:148:1.8.2.2 - deposit: vccgnd_splitnet....

{SP5} (Xilinx Answer #10312): 3.1i Virtex PAR - Dr. Watson Error
"0xC0000005 0x0693628F7" when implementing ChipScope core.

{SP4} (Xilinx Answer #8992): 3.1i XFLOW - ERROR:Trace:19 - Unable to
access design file after Control-C (Ctrl-C) is used to interrupt PAR.

{SP4} (Xilinx Answer #9437): 3.1i Virtex-E PAR - Placer crashes while
handling range constraints on IOBs.

{SP4} (Xilinx Answer #9873): 3.1i Virtex-E PAR - Placer rejects placement
of slices containing F5/F6 muxes.

{SP4} (Xilinx Answer #10256): 3.1i Virtex-E PAR - Problem with DLLIOB
Select I/O input and placement.

{SP4} (Xilinx Answer #10255): 3.1i Virtex PAR - Long PWR/GND run times
have been seen for Virtex designs.

{SP4} (Xilinx Answer #10116): 3.1i PAR - PAR runs out of memory.

{SP3} (Xilinx Answer #9372): 3.1i XC5200 PAR - MPPR PAR runs crash on
second pass for 5200 designs.

{SP3} (Xilinx Answer #9725): 3.1i Virtex-E PAR - PAR takes a long time
during the "Generate PAR statistics" phase.

{SP3} (Xilinx Answer #9484): 3.1i PAR - Guided PAR fails with the error:
Place:489 The clock group consisting of the following components ...

{SP3} (Xilinx Answer #10049): 3.1i Virtex-E PAR - The router doesn't
always use a long line when one is available.

{SP2} (Xilinx Answer #9732): 3.1i Virtex PAR - Problem with data file
causes v300cb228 design to get internal error.

{SP2} (Xilinx Answer #9729): 3.1i Virtex PAR - Router crash during
PWR/GND routing.

{SP2} (Xilinx Answer #9519): 3.1i Virtex-E PAR - INTERNAL_ERROR:Place:
baspltaskmincut.c:453:1.12 - Matcher did not find a solution.

{SP1} (Xilinx Answer #9589): 3.1i Virtex PAR - Guided PAR fails with
ERROR:Portability:3 - This Xilinx application has run out of memory.

{SP1} (Xilinx Answer #9588): 3.1i Virtex PAR - Range constraint expansion
in Modular Design uses too much memory.

{SP1} (Xilinx Answer #9359): 3.1i Virtex PAR- Illegal pin swaps may occur
on address pins of SRL16E.

{SP1} (Xilinx Answer #9587): 3.1i XC4000XLA PAR - Pad report does not
report all the Vcc pins for XC044XLA-HQ304.

{SP1} (Xilinx Answer #9345): 3.1i Virtex PAR - Placer crashes on designs
with RPM macros containing Block RAM.

{SP1} (Xilinx Answer #9250): 3.1i Virtex-E PAR - PAR runs out of memory
on a design with offset in constraints.

{SP1} (Xilinx Answer #8937): 3.1i Virtex PAR - PAR hangs during PWR/GND routing.

PROJECT NAVIGATOR

{SP7} (Xilinx Answer #10886): 3.3i Foundation ISE - "Enable Verilog Preprocessor"
property doesn't work.

{SP7} (Xilinx Answer #10885): 3.3i Foundation ISE - "Enable Verilog Preprocessor"
property doesn't work.

{SP7} (Xilinx Answer #10884): 3.3i Foundation ISE - Templates are missing from the
Project Navigator Language Assistant.

{SP7} (Xilinx Answer #10883): 3.3i Foundation ISE, Synplify - Floppy Drive (a:) is
accessed during synthesis. (Windows 98)

{SP7} (Xilinx Answer #10486): 3.3i Foundation ISE, Synplify - Remote sources will
not work in the Synplify flow.

{SP6} (Xilinx Answer #10236): 3.1i Foundation ISE, Project Navigator - Exit Code 0001
caused after changing constraints.

{SP5} (Xilinx Answer #10415): 3.1i WebPACK/Foundation ISE - Double-click edit doesn't
work for ABEL Test Vectors.

{SP5} (Xilinx Answer #10228): 3.1i Foundation ISE - Online Help for Waveform Viewer in
Foundation ISE 3.1 is missing.

{SP4} (Xilinx Answer #10225): 3.1i Foundation ISE - Project Navigator
does not support ABEL test vector (ABV) files.

{SP4} (Xilinx Answer #10226): 3.1i Foundation ISE - Addition of a VHDL or
Verilog source causes Project Navigator to hang.

{SP4} (Xilinx Answer #10227): 3.1i Foundation ISE - Running MPPR from
Foundation ISE causes the PC to hang.

{SP4} (Xilinx Answer #10204): 3.1i Foundation - Question marks appear on
Design Entry and Synthesis toolbox after implementation.

{SP3} (Xilinx Answer #9721): 3.1i Foundation ISE- MTI Error: Cannot open
macro file: top.vfd' - this file is not created.

{SP3} (Xilinx Answer #9722): 3.1i Foundation ISE - "Insert I/O Pads" not
working with FPGA Express flow.

{SP2} (Xilinx Answer #9388): 3.1i Foundation ISE - Double-clicking on XCO
file from within Project Navigator fails.

PROM FILE FORMATTER

{SP3} (Xilinx Answer #9708): 3.1i PROM File Formatter - Spartan-II PROMs
are not selectable (17S50XL, 17S100XL, 17S150XL, 17S200XL)

{SP3} (Xilinx Answer #10034): 3.1i PROM File Formatter - 18v00 parts
should be listed in PROM device list.

{SP3} (Xilinx Answer #9569): 3.1i PROM File Formatter - 17S05XL is listed
with the wrong size.

{SP2} (Xilinx Answer #9708): 3.1i PROM File Formatter - Spartan-II PROMs not
selectable.

SCHEMATIC CAPTURE

{SP4} (Xilinx Answer #10279): 3.1i Foundation - Exporting design netlist
causes GPF in module conv_acs.dll

SPEED FILES

{SP7 & SP6} (Xilinx Answer #10359): 3.1i Speed Files - WARNING: Timing:180
-Pulse- width error at comp "maindll".

{SP6} (Xilinx Answer #10582): 3.1i Virtex-E Speed Files - A speed modeling problem
that affected the clock skew has been fixed.

{SP6} (Xilinx Answer #10581): 3.1i Virtex-E Speed Files - New speed models have been
added for Virtex-E global clocks.

{SP6} (Xilinx Answer #10395): 3.1i Spartan-II Speed Files - ADVANCED MINs for Spartan-II
are now available.

{SP6} (Xilinx Answer #9327): 3.1i Virtex-E Speed Files - LVDS input feeding DLL with internal
feedback needs additional 0.5 ns delay

{SP4} (Xilinx Answer #10258): 3.1i Speed Files - Speed File changes for 3.2i SP4.

{SP3} (Xilinx Answer #10054): 3.1i Virtex-E Speed Files - ERROR:Trace:1 - Invalid speed
"min" specified on command line.

{SP3} (Xilinx Answer #10055): 3.1i Spartan-II Speed Files - PRELIMINARY
-5 files are available for Spartan-II

{SP2} (Xilinx Answer #9704): 3.1i Virtex Speed Files - New Virtex Speed Files are available.

TIMING

{SP7} (Xilinx Answer #10905): 3.3i Timing Analyzer - Prorating Temperature for Virtex
gives varying results.

{SP7} (Xilinx Answer #10520): 3.1i TRCE - XML timing report is not automatically
generated by default.

{SP6} (Xilinx Answer #10264): 3.1i Timing Analyzer - Custom analysis brings up an
empty report for CPLDs.

{SP4} (Xilinx Answer #9619): 3.1i FPGA Editor - Core dumps when
specifying IOBs to drive '0'.

{SP3} (Xilinx Answer #9297): 3.1i Timing - Multi-Cycle (FROM:TO) path
constraint is getting picked up by PERIOD constraint.

{SP1} (Xilinx Answer #3513): 3.1i Timing Analyzer - GDI resources taken
up when scrolling on a report.

UNISIM

{SP6} (Xilinx Answer #10578): 3.1i UNISIM - CLKDLLHF does not activate LOCK without a
reset pulse in simulation. (Verilog)

{SP6} (Xilinx Answer #10577): 3.1i Mentor SIMPRIM - INIT property is missing on X_LUT4,
X_LUT3 and X_LUT2 symbols.

{SP6} (Xilinx Answer #9215): 3.1i Virtex-E UNISIM - CLKDLL doesn't lock in simulation if
Clock remains low for one period upon start of simulation.

{SP6} (Xilinx Answer #10469): 3.1i UNISIM and SIMPRIM - Output of Dual-Port Block
RAMs do not reset when RST is asserted and there is a collision.

{SP5} (Xilinx Answer #10414): 3.1i UNISIM - Overlap of memory space in the
unisim_VITAL_RAMB16_S9_Sx models. (VHDL)

XST

{SP7} (Xilinx Answer #10899): 3.1i XST - XST aborts with an internal error when a certain
Verilog parameter construct is used.

{SP7} (Xilinx Answer #10898): 3.1i XST - XST output fails in simulation for designs that
contain certain array constructs.

{SP7} (Xilinx Answer #10897): 3.1i XST - "ERROR:NgdBuild:432 - logical block
'ram_instance' with type 'RAM64X2S_1' is unexpanded".

{SP7} (Xilinx Answer #10894): 3.1i XST - XST will often issue an internal error when record
types are used.

{SP7} (Xilinx Answer #10896): 3.1i XST - XST Support for translate_off/translate_on
constraints in VHDL.

{SP6} (Xilinx Answer #10573): 3.1i XST - VERILOG synthesis: XST hangs at 50% when
synthesizing a Verilog file.

{SP6} (Xilinx Answer #10572): 3.1i XST - XST rejects a valid Verilog operator % (VLG__2008).

{SP6} (Xilinx Answer #10571): 3.1i XST - Crashes with Dr. Watson error: "c00000fd (stack
overflow)" when "Add I/O buffers" is de-selected.

{SP6} (Xilinx Answer #10570): 3.1i XST - XST hangs after the line: "Extracting 1-bit register
for internal node."

{SP6} (Xilinx Answer #10082): 3.1i XST/WebPACK - Project Navigator hangs while synthesizing
a HDL file and XST.EXE keeps on running.
AR# 10902
日期 09/20/2002
状态 Archive
Type 综合文章