AR# 10964


3.1i CORE Generator - Multiplier Generator v3: Sequential type: gives incorrect output results.


Keywords: CORE Generator, COREGen, multiplier, mult_gen_v3, sequential,
output width.

Urgency: Standard

General Description:
When using Xilinx CORE Generator Multiplier v3_0 with type set to
"sequential," the correct output result may not be given if the output
width is less than the minimum required width.


When using the sequential multiplier, the minimum required output width
can be calculated using the following formula:

if c_b_type = signed,
width = c_baat+c_b_width+1+(c_baat*(number_clocks-1));
else if c_b_type = unsigned,
if c_b_width = 1,
width = c_baat+mult_signed+1+(c_baat*(number_clocks-1));
width = c_baat+c_b_width+mult_signed+1+(c_baat*(number_clocks-1));


c_b_type = sign type of b input
width = minimum output width required
c_baat = round-up ( c_a_width/clk_cycles_per_input)
c_b_width = width of b input
number_clocks = clk_cycles_per_input
mult_signed = 1 if c_a_type is signed or controlled_by_pin, 0 otherwise

(Every successful core generation will output a core_name.xco file that will
contain the above parameters.)

If an output width smaller than above required number is selected, the multiplier
will automatically drop the least significant bits to reach the selected output width.
This may result in an undesired output result.

This general rule may result in larger output widths than are actually required. Even
if this is the case, you must still select the minimum output size, but only the
required least significant bits need to be connected to the rest of the circuit.
AR# 10964
日期 08/23/2002
状态 Archive
Type 综合文章
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