AR# 10972


Virtex-II/Pro FPGA, DCM - What do the various status pins represent?


What do the various status pins represent?


Please see the Virtex-II/Pro FPGA data sheets.

Virtex-II Pro:
Module 2 -> Functional Description:FPGA -> Digital Clock Manager (DCM)

Module 2 -> Detailed Description -> Digital Clock Manager (DCM)

The DCM Status Pins table lists the following:

Status <0> represents the phase shift overflow.
Status <1> represents CLKIN stopping.
Status <2> represents CLKFX stopping.
Status <3> through <7> are N/A.

NOTE: Status<0>: Please see (Xilinx Answer 12378) for more information on phase shift overflow.

Status<1>: After the clock is lost, there is a several-cycle latency before the Status<1> pin goes High. This occurs within 1-8 CLKIN clock cycles if any single rising edge of CLKIN does not arrive at the expected time (within a +/- one half clock cycle window).

Once another rising edge arrives, the "DLL CLKIN Stopped" (Status<1>) signal goes Low again within 1-8 CLKIN clock cycles. The cycle latency depends upon frequency, with higher frequency clocks leading to greater latency. The DCM resumes functionality when the clock resumes.

The DCM may or may not lose the LOCKED signal if the CLKIN is stopped for a short period. If DCM loses the LOCKED signal, you must reset the DCM for it to resume functionality. For more information, please see the "DCM" section in Module 2 of the Virtex-II/Pro User Guide (linked above).

Status<2>: If you are using the CLKFX or CLKFX180 outputs, and the wrong CLKIN cycle is skipped (or if CLKIN stops altogether), the CLKFX/FX180 outputs will freeze, and will not recover without a reset. The "CLKFX Stopped" status signal has been added so that this situation is easier to recognize. Once it asserts, it will not de-assert until the DCM is reset.
The "CLKFX Stopped (Status<2>)" signal is supported in all Virtex-II ES, C, and I devices.
AR# 10972
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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