We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10975

3.1 System Generator for DSP - How can I implement an absolute value using the System Generator?


General Description:

I want to implement a "conditional" 2's complement function in the Math section. I want an absolute value, which is not a difficult function, but I do not know how to get a decent implementation using the System Generator.


You can do this using a mux and negate operator. Strip off the MSB using a slice block, and use this to drive the select line of the Multiplexer. The two inputs to the Mux are the original signal and also the 2's complement of the signal. Consequently, if negative, the 2's complement value is selected and if positive, the value passes through unchanged. Also, this function can be pipelined at minimal cost to increase performance. You can then save this as a subsystem in your own library as an "abs" block and you can reuse it whenever necessary.

AR# 10975
日期 12/15/2012
状态 Active
Type 综合文章