When targeting the PCI v3.x Core to a Virtex-II, Virtex-II Pro, or Spartan-3, the following error occurs during MAP:
"ERROR:LIT:163 - Virtex PCILOGIC macro PCILOGIC symbol "PCI_LC/OUT_CE/MAGICBOX" (output signal=PCI_CORE/PCI_LC/OUT_CE/HARD_CE) is an invalid component in Virtex2 architecture."
This error occurs when specialized logic is enabled in the core and the target device is a Virtex-II, Virtex-II Pro, Virtex-4. This logic is referred to as "PCILOGIC." Only Virtex, Virtex-E, Spartan-II/E, and Spartan-3/E/A devices contain this specialized logic. Note, that even though the Spartan-3 contains the PCILOGIC resource it is not used with the core. This specialized device resource is used to generate the output clock enable signal. For more information on when to use the specialized PCILOGIC resource, refer to the "Datapath Output Clock Enable" section of the Initiator/Target v3.1 for PCI Getting Started Guide." There are four possible solutions to this issue:
Set Bit 251 in the cfg.v or cfg.vhd file to a logic "1" instead of a logic "0". Setting Bit 251 to logic "1" turns off the use of PCILOGIC.
This error occurs because two options for the generation of the output clock enable are available; you can use either generic resources (LUTs) or the specialized PCILOGIC. Bit 251 of the configuration file is used to select between the two. In Virtex, Virtex-E Spartan-II/-IIE, and Spartan-3A/-3E, either option is appropriate. For high-speed operation, the PCILOGIC is better for timing purposes. However, there are only two PCILOGICs available per device; one on the left side and one on the right. For example, if you want four cores in a V2000E device, only two of them can use the PCILOGICs; the other two must use the generic option.
In Virtex-II, Virtex-II Pro, Virtex-4, and Spartan-3 only the generic option is appropriate because the PCILOGIC resource is not needed and does not exist in the Virtex-II/Pro/4 architecture. If PCILOGIC is enabled in the core, the above error occurs.
If this issue is occurring with the PING example, then you must edit the "ping_cfg.vhd" or "ping_cfg.v" file. These files are located in the /example/source directory. As previously described, bit 251 must be set to "1" for Virtex-II, Virtex-II Pro, Virtex-4, and Spartan-3.
If setting Bit 251 to a Logic "1" does not solve the problem, ensure that the "-u" switch is not being used in MAP (the "-u" switch is used to instruct the mapper to not trim unconnected logic). For the PCI Core to work correctly, the mapper must remove the PCILOGIC in the Core for a Virtex-II, Virtex-II Pro, Virtex-4 and Spartan-3 device. If the "-u" switch is removed, the error will not occur.
This error can occur when using ISE 10.1 due to a SAVE flag set on the PCILOGIC instance within the core's netlist. In this case, you must add the XIL_MAP_OLD_SAVE environment variable, set to a value of "1." The core netlist will be updated in ISE 11.1 to prevent this issue.
This error can occur when using PCI Monitor signals in ChipScope on Virtex-4 device. To use ChipScope to debug the signals originally available in PCI Monitor, users must use the actual signals (not the one from PCI Monitor) and scope it right after the Flip Flop (FDPE).
05/14/2008 - Added Solution 4 and general updates.
9/14/2012 - Added information regarding the use of ChipScope on PCI Monitor signals in V4 devices.