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AR# 10994

3.x FPGA Express - When I use the `include statement in Verilog files, relative or absolute files are not recognized.

描述

Keywords: 3.1i, FPGA Express, fe_shell, Verilog, include, relative, paths

Urgency: Standard

General Description:
FPGA Express will not recognize absolute or relative paths while using the
`include statement in Verilog files. Examples of this are:

`include "c:\project\module.v"

or

`include "..\..\module.v"

解决方案

You must have all of the Verilog files in the same directory so that the `include
statement will look like:

`include "module.v"

AR# 10994
日期 08/11/2003
状态 Archive
Type 综合文章
的页面