We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1104

MAKEBITS TIE--Should all designs be tied?


Keywords: makebits tie recommendation

Urgency: standard

General Description:
The question often comes up as to what Xilinx's official
position is as far as the tying of designs. Some
considerations are listed below.


The main reasons for tying a design are to reduce power
consumption caused by floating internal nets, and to
reduce sensitivity of the programmed device to noise.
The MakeBits tie option defines all unused CLB and IOB inputs
and consumes all available interconnect. This guarantees that
all unused resources are at a known, non-floating logic level.

Tying a design is generally recommended for production
designs. On the other hand, it is not critical to tie a
design during the debugging stage of the design process unless
it is a power-critical application. Skipping the tie
operation during debug can save processing time.

The general rule is: tie production designs whenever possible
to reduce power consumption and internal noise.

It should be noted that it may not always be possible to tie
down a design due to a lack of resources or routing
congestion. From a functionality standpoint, tying the design
may also not be desirable if the delay associated with tying
unused interconnect to certain signals slows them down to
unacceptable levels. The solution in such cases is to tell
Makebits to avoid using certain nets for Tie by marking them
as Critical before the Makebits -t is run.

Note also that tie remains an all-or-nothing process in
Makebits--that is, if it is not possible to tie off *all*
unused interconnect, *none* of the unused interconnect will
be tied. This applies to all versions of Makebits up to

AR# 1104
日期 10/01/2008
状态 Archive
Type 综合文章