General Description: The CORE Generator customization GUI for Dual or Single Port Block Memory V3.0 includes an information panel that shows "Read Pipeline Latency." However, the simulation result reports a different latency than the information panel.
The CORE generator information panel is correct; however, the simulation result is correct as well. This problem is a matter of how one interprets "latency."
The latency basically indicates when you can sample your output data. The correct way to calculate the latency is to count the active lock edges after the actual clock where the operation takes place to the clock edge in which the output can be sampled.
The latency is often mistakenly considered the cycle in which the output will become available.
Following example will show a multiplier which has latency = 4. (The output can be sampled at the 4th clock edge, after the operation takes place.)