AR# 11169

描述

Foundation, ISE, 3.1i, HDL, Converter

General Description:

When trying to convert an ABEL/AHDL file into VHDL using the HDL

Converter in Foundation ISE the output file created is always a Verilog file.

解决方案

The only known workaround to this problem is to run the XPORT

program from the command line using the -VHDL switch.