General Description: In a Spartan-II design, the customer has both an FDS with INIT=R and an FDR with INIT=S, but these are getting mapped into the IOB, which causes the incorrect logic to be produced as follows:
FDS with INIT=R results in an FDR in the IOB FDR with INIT=S results in an FDS in the IOB
However, this is correctly implemented when it is in the CLB.
In the hardware, IOB register elements have a single pin for SR (please see FPGA Editor).
Since the register element has one pin for SR, the INITSTATE determines whether the hardware sets or clears the register when the SR signal goes high. For IOB registers, the user-assigned value for INITSTATE has precedence over whether the logical symbol was FDR or FDS. This is a hardware limitation.
Note that the SLICE hardware is different, as registers have two pins related to SR functionality.
This is an issue for customers who might override the default INITSTATE for I/O registers. The work-around is to put IOB=FALSE on such registers
The software will be changed in the first major release after 4.1i to have the following behavior:
- If the register has an INITSTATE contrary to SR connectivity, the Virtex packer should not pack the register into an IOB. - Additionally, if the register is directed to an IOB, the Virtex packer should generate a user error.