UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11277

4.1i TRCE/Timing Analyzer - Timing errors are reported in timing analysis even though TIGs are applied

描述

General Description:

I have applied TIGs to all paths between two different clock domains, but a timing error is still reported.

解决方案

If you are using path TIGs, eliminate the desired paths from timing analysis by using net/pin TIGs instead of path TIGs.

This issue will be fixed in the 5.1i software, which is scheduled to be released in September, 2002.

AR# 11277
日期 01/18/2010
状态 Archive
Type 综合文章
的页面