AR# 11329: 3.1i CORE Generator - Single/Dual-Port Block Memory generation reports "FATAL: Port S: external net width (7) does not match the port width (6)."
AR# 11329
3.1i CORE Generator - Single/Dual-Port Block Memory generation reports "FATAL: Port S: external net width (7) does not match the port width (6)."
General Description: In CORE Generator, when I generate a block memory core (single- or dual-port) in v3_0 or v3_1, the following error message appears:
FATAL: Port S: external net width (7) does not match the port width (6). ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com. java.lang.RuntimeException at java.lang.Throwable.<init>(Compiled Code) at java.lang.Exception.<init>(Compiled Code) at java.lang.RuntimeException.<init>(Compiled Code) at com.xilinx.sim.base.Port.setExternNet(Compiled Code) at com.xilinx.sim.base.Port.<init>(Compiled Code) at com.xilinx.sim.base.Port.<init>(Compiled Code) at com.xilinx.sim.base.Sim.addBusPort(Compiled Code) at com.xilinx.ip.baseblox_v2_0.C_MUX_BIT_V2_0.addMuxBitPorts(Compiled Code) at com.xilinx.ip.baseblox_v2_0.C_MUX_BIT_V2_0.implement(Compiled Code) ... ... ... at com.xilinx.xcc.synth.util.Netlister.main(Compiled Code) Exception in thread "main"
解决方案
This problem occurs only on certain width/depth size combinations.
For example:
Virtex
Width (A|B) = 8 Depth (A|B) = 33204
Virtex-II
Width (A|B) = 9 Depth (A|B) = (33204*4)
A possible work-around is to use different width/depth sizes. This issue was fixed in Block Memory v3_2, which was released in 3.1i_ip_update #4 (May, 2001).