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AR# 11572

3.1i CORE Generator - Known Issues in the 3.1i/3.2i IP Update #4 (D_IP4).


Keywords: D_IP4, 3xi_ip_update4, release note, COREGen, DA, FIR, filter, sine, cosine, lut, lookup, table, Virtex, adder, subtracter, FD, based, shift, register, accumulator, Virtex-II, block, RAM, memory, problem, single-port, dual-port, block memory, Asynchronous FIFO, release notes, distributor memory, FFT, 32i_ip_update_4, CORE Generator

Urgency: Standard

General Description:
This answer record addresses known issues in the 3xi_ip_update4 file (also referred to as "D_IP4").



Software Compatibility

The D_IP4 IP update is only compatible with Xilinx CORE Generator v3.1i, which is included with Alliance v3.1i, Foundation v3.1i and Foundation ISE v3.1i software. This IP update is also compatible with v3.2i , v3.3i, and subsequent releases. This IP update should not be used with any other versions of CORE Generator (such as v2.1i or earlier); in addition, it should not be used with v4.1i.

Service Pack Requirement

D_IP4 has been tested with Xilinx software v3.1i and Service Pack 8. The latest service pack for v3.1i is available at: http://support.xilinx.com/support/techsup/sw_updates/

Previous IP update Requirement

D_IP4 update is cumulative; therefore, previous IP updates are not required. If you are a Workstation user and have already installed 3.1i_ip_update1 (D_IP1) on your system, your system administrator may need to change the permissions on your current CORE Generator installation before you install the D_IP4 update. This can be done using the following command:

chmod -R u+w $XILINX/coregen

Acrobat Reader Requirement

Acrobat Reader version 4 or later must be installed in order to correctly view ore data sheets. Acrobat software can be downloaded from the following Adobe site:


Distributed Memory v4_1

1. When large Distributed Memory (C_DIST_MEM_V4_1) cores are generated, there is a possibility that the design will fail when it passes through BitGen. This failure occurs because PAR does not insert buffers to signals that have very large fanouts. In Xilinx Service Pack 8, PAR has been updated to eliminate this problem. The latest service pack for v3.1i is available at: http://support.xilinx.com/support/techsup/sw_updates/

2. The placer will occasionally reject valid Virtex-II DPRAM macros, including some defined by CORE Generator. The errors posted begin with the message:

v2_dpr_32X16_INST/hset" may not be placed in such a way that it can be routed.

Please see (Xilinx Answer 10505).

3. The parameters for the Distributed Memory core have changed between "dist_mem_v3_x" and "dist_mem_v4_x"; therefore, the .xco files are no longer compatible.

Please see (Xilinx Answer 11600).

4. Generating the 1D DCT (Discrete Cosine Transform) on Solaris machines may cause a core dump.

Please see (Xilinx Answer 11624).
AR# 11572
日期 08/23/2002
状态 Archive
Type 综合文章