General Description: This answer record addresses known issues in the 3xi_ip_update4 file (also referred to as "D_IP4").
GENERAL KNOWN ISSUES
The D_IP4 IP update is only compatible with Xilinx CORE Generator v3.1i, which is included with Alliance v3.1i, Foundation v3.1i and Foundation ISE v3.1i software. This IP update is also compatible with v3.2i , v3.3i, and subsequent releases. This IP update should not be used with any other versions of CORE Generator (such as v2.1i or earlier); in addition, it should not be used with v4.1i.
D_IP4 update is cumulative; therefore, previous IP updates are not required. If you are a Workstation user and have already installed 3.1i_ip_update1 (D_IP1) on your system, your system administrator may need to change the permissions on your current CORE Generator installation before you install the D_IP4 update. This can be done using the following command:
1. When large Distributed Memory (C_DIST_MEM_V4_1) cores are generated, there is a possibility that the design will fail when it passes through BitGen. This failure occurs because PAR does not insert buffers to signals that have very large fanouts. In Xilinx Service Pack 8, PAR has been updated to eliminate this problem. The latest service pack for v3.1i is available at: http://support.xilinx.com/support/techsup/sw_updates/
2. The placer will occasionally reject valid Virtex-II DPRAM macros, including some defined by CORE Generator. The errors posted begin with the message:
ERROR:Place:1809 - RPM "TCP_FPGA_CORE_INST/DPR_32X16_INST/ v2_dpr_32X16_INST/hset" may not be placed in such a way that it can be routed.