We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11635

5.2i CPLD TSim - The bit order of certain busses is reversed in back-annotated (timing) simulation


Keywords: 5.2i, 5.1i, 4.2i, 4.1i, 3.1i, WebPACK, Fitter, CPLD, bus, reverse, backanno, simulation

Urgency: Standard

General Description:
In my back-annotated timing simulation file, busses coded in an "X to Y" notation (as opposed to a "Y downto X" notation) are reversed.

For example:

Given a bus coded in VHDL as follows:
din : in std_logic_vector (0 to 3);

The resulting time_sim.vhd file shows that the bus order has been changed to:
din : in std_logic_vector (3 downto 0);

This will obviously create problems with timing simulation testbenches.


You can work around this issue in two ways:

1. Change the bus-ordering from (x to y) to (y downto x).
2. Create a separate testbench for functional and timing simulation.

This issue will be fixed in 6.1i.
AR# 11635
日期 08/13/2009
状态 Archive
Type 综合文章