AR# 11695

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5.1i xilinx2primetime - How to get temperature and voltage prorate in the SDF?

描述

General Description:

How can I get the SDF from xilinx2primetime have values that reflect the temperature and voltage prorating that was done in implementation?

解决方案

You have brought up a very important topic here. In order to generate the

proper SDF file reflecting a specific T & V (Temperature, Voltage), we need to

run the NGDANNO with -p switch. The -p switch reads in the PCF file which

contain the desired T and V.

This means that you need a specific set of SDF, Verilog Netlist for each pair of

T V. I will ask Raj to create for you two sets of Netlist and SDF for the

following V and T :

T = 85C

V = 1.70V

T = 40C

V = 1.90V

Raj, please proceed to modify PCF file with each set of T an V and send the

resultant Verilog and SDF file to John.

Shiv, please make sure this feature is placed into the regression suite.

Chris, please add a Solution Record to cover this.

Thanks,

Hamid

"Vargas, John B." wrote:

> Raj,

>

> I was analyzing the jtag paths more in detail today and I was able to

> compare point by point with trace. I can see that the output from the 5.1i

> ngdtover and xilinx2primetime which is annotated into primetime is

> completely incorrect, but the one you sent has values that are more similar

> to the trace values.

>

> 4) This means that we can't do anything with primetime except with your

> converted files. Do you know when we can get a version of our own where we

> can do the conversion?

>

> 5) Even with the files you sent, the data is still not the same, though.

>

> For example for the following path in the files you sent back:

> DefineEndpoints FromFFs

> UUT/MPT/proc/isystem/icore_chip/ijtag_port/i_debug_port/dati_latch[2]

> DefineEndpoints ToFFs

> UUT/MPT/proc/isystem/icore_chip/ijtag_port/i_debug_port/shift_register[2]

>

> TRACE 85C/1.70V = 10.635ns

> TRACE -40C/1.90V = 5.487ns

> However Primeime (-max and -min) = 14.01ns

>

> If I do a report_lib on the simprims library I get

> Operating Conditions:

>

> Name Process Temp Voltage Tree Type

>

> ---------------------------------------------------------------------------

> WCCOM 1.00 70.00 4.75 worst_case

>

> So, how do I run the Primetime analysis on a specific set of

> temperature/voltage conditions that match the trace values?

>

> -John V.

>

> -----Original Message-----

> From: Vargas, John B.

> Sent: Thursday, February 13, 2003 12:55 PM

> To: 'Raj Klair'

> Subject: RE: Primetime translation

>

> Raj,

>

> 1) Thanks very much for the translation. I have been looking into it and now

> I don't see the hold errors in the Jtag area that was in the previous one.

> This is good news, but not the end of the story because this ncd had a

> working jtag. I have attached one more set of files for a version of this

> design (same ngd) that was simply re-placed and routed and ended up with

> failing jtag. If you could translate this one, then we will have a good

> sample of the same design and one that fails and one that passes.

>

> 2) I tried to use the same constraints file (sdc) you provided but with an

> .sdf and .v file that I generated with 5.1i. I get different results from

> the same source files. With the 5.1i ngd2ver and xilinx2primetime I do get

> hold errors on the jtag and with your translation I don't.

>

> Could you explain what is different about the new SDF and V files that you

> are generating?

>

> 3) I do see some setup errors that I can't explain, I am trying to time the

> same path

> with primetime and trace. I will send you more details on that soon.

>

> -John V.

>

> -----Original Message-----

> From: Raj Klair [mailto:rvklair@xilinx.com]

> Sent: Tuesday, February 11, 2003 6:39 PM

> To: Vargas, John B.

> Subject: Re: Primetime translation

>

> John,

>

> Please find enclosed the design with the files (unisys.tar.gz).

> The files are built from the fpga_top_pins.ngd and the c4ft....ucf

>

> 1. For TIMEGRP spi_inputs OFFSET OUT .. AFTER has been applied on the

> INPUT ports (you may use OFFSET IN .. BEFORE for these ports).

>

> These input ports are :-

>

> spi_moe_l_p

> spi_exint_l_p

> spi_ram_we_l_p[3]

> spi_ram_we_l_p[2]

> spi_ram_we_l_p[1]

> spi_ram_we_l_p[0]

> spi_mreq_l_p

> spi_exrdy_l_p

>

> 2. PERIOD is defined on internal nets. These are :-

>

> fsynci_pz (changed manually to fsynci_pz in fpga_top_pins.sdc)

> mp_jt_tckz ( changed manually to mp_jt_tck in fpga_top_pins.sdc)

>

> Please feel free to contact me if you need more assistance in this

> regard.

>

> regards,

>

> Raj

>

> "Vargas, John B." wrote:

> >

> > Raj,

> >

> > I wondered if have an update on the translation. Are you running into

> > problems? Anything I can help with?

> >

> > Also any news on the differences between trace and primetime for the last

> > netlist with respect to the hold violations?

> >

> > -John V.

> >

> > -----Original Message-----

> > From: Hamid Agah [mailto:Hamid.Agah@xilinx.com]

> > Sent: Sunday, February 09, 2003 1:05 AM

> > To: Vargas, John B.

> > Cc: Raj Klair; Chris Zeh

> > Subject: Re: Primetime translation

> > Importance: High

> >

> > Hi John,

> >

> > 1. Raj Klair is working on your designs and should be able to provide you

> > with the new netlist,

> > SDC, SDF files hopefully by Monday. Raj, please validate the files and

> then

> > forward them to

> > John. PLease also include the .twr (PAR report) as well.

> >

> > 2. While I am away, please contact Chris Zeh @ (chris.zeh@xilinx.com) for

> > further follow up on

> > PrimeTime issues.

> >

> > I will return on 2/20.

> >

> > HAmid

> >

> > "Vargas, John B." wrote:

> >

> > > Hamid,

> > >

> > > I am finally starting to time with Primetime and I am seeing different

> > > results than the trace tool. I would like to do an effort to correlate

> the

> > > designs by timing the same paths and analyzing the segment delays in

> > detail.

> > > However, we have changed the design and the constraints significantly

> from

> > > the one you processed for us.

> > >

> > > Attached is a new constraints file. Could you have this translated?

> > >

> > > Also, can I perform the SDF file creation with the translator version I

> > have

> > > and then use your updated constraints? Or do I need you to do that too?

AR# 11695
日期 01/18/2010
状态 Archive
Type 综合文章
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