We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11736

4.2i Foundation - Virtex-II, DCM- When I use a DCM on a schematic Virtex-II design, a change in the M and D values does not appear in simulation


Keywords: Virtex-II, DCM, schematic, attribute, clock, divide, CLKDV_, CLKFX_, DIVIDE, MULTIPLY

Urgency: Standard

General Description:
When I use a DCM on a schematic Virtex-II design, and I change the CLKDV_DIVIDE or CLKFX_DIVIDE, the CLKFX_MULTIPLY, etc., the new parameters do not affect the simulation. The simulations are always set to the default vales of M = 4 and D = 1.


DCM Parameters are contained in the EDIF file in the form of "Property" statements. The Logic Simulator does not does not read these attributes, so it is unable to simulate these parameterized functions.

If you wish to simulate these device features, you must use a different simulator.
AR# 11736
日期 08/11/2003
状态 Archive
Type 综合文章