General Description: Are there restrictions on IBUFG, DCM, and BUFG routing in Virtex-II devices? Are these restrictions the same between ES silicon and production devices?
(In Engineering Sample (ES) silicon, within a quadrant, there is only dedicated routing from IBUFGs to DCMs or BUFGs. Therefore, if you feed a clock into an IBUFG in Quadrant 1, it can only feed the DCMs or four BUFGs in that same quadrant. If you try to use DCMs or BUFGs in another quadrant, local routing is used, so you will see much larger delays than with dedicated routing.)
Yes, there are restrictions on IBUFG-DCM-BUFG routing in Virtex-II. The restrictions on IBUFG-DCM routing in ES and production devices are different, and the restrictions on DCM-BUFG routing in ES and production devices are the same.
In an engineering sample, due to the lack of interconnection across different quadrants, an IBUFG and any connected DCM must be constrained (via the constraints file) to be in the same quadrant for proper functionality.
In production devices, all eight IBUFGs have dedicated routing to all DCMs on the same edge (top or bottom) of the device. (Please see the figure below.) This restriction will be correctly checked by the software in 4.1i Service Pack 3. For more information, see (Xilinx Answer 12719).
Generally, each DCM can connect to a maximum of four BUFGs. There are pairs of buffers with shared dedicated routing resources such that if both are driven by the same DCM, one of the two will necessarily be driven using non-dedicated routing resources; this causes the design to fail. If the buffers are numbered 1 through 8 from left to right, there are four pairs of exclusives: 1:5, 2:6, 3:7, 4:8. If a buffer is placed in Site 1, another driven by the same DCM should not be placed in Site 5 (please see the figure below). This restriction will be checked by the software in 4.1i Service pack 1. For more information, please see (Xilinx Answer 12246).
The DCM-BUFGMUX routing restriction is a superset of DCM-BUFG routing, as a BUFG is implemented with a BUFGMUX configured to always select input I/0. The figure below describes the complete available routing resources on an IBUFG-DCM-BUFGMUX connection.
IBUFG-DCM-BUFGMUX routing restriction
NOTE: In the 4.1i software, you are required to set the environment variable XIL_BITGEN_VIRTEX2ES to produce the correct bitstream for both ES and production silicon. (Please see (Xilinx Answer 12326) for more information).
This environment variable will turn on the DRC to check IBUFG-DCM routing, even in production silicon. This is addressed further in (Xilinx Answer 12719).