We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11766

9.1i PrimeTime/Timing Analyzer/Virtex-II/Virtex-II Pro - Timing Analyzer and PrimeTime report different OFFSET slacks for two-phase clocks


For OFFSETs with both positive and negative edge flip-flops, TRCE incorrectly calculates slack for negative-edge flip-flops. This causes problems with the correlation of Trace and PrimeTime simulations.


TRACE calculates offset slacks for two-phase clocks by basing the calculation on the respective edges. PrimeTime, on the other hand, bases its slack calculation on only the rising clock edge for both positive- and negative-edge flops.

To remedy this issue, create a group and OFFSET it for the positive set of flip-flops; create another group and OFFSET it for the negative-edge flip-flops.

This issue will be fixed in the next major software release.

AR# 11766
日期 01/18/2010
状态 Archive
Type 综合文章